This invention relates to a flash memory test system which tests and evaluates flash memories, and more particularly, to a flash memory test system which tests write and erase performance of a flash memory, counts the numbers of times of write or erase operations required until the data is successfully written or erased for each address of the flash memory, and processes and analyzes the acquired data and displays the distribution of the numbers of times with respect to the physical locations in the flash memory.
A flash memory is a non-volatile IC memory which belongs to a category of programmable read only memories (PROM) whose data therein is rewritable. A flash memory has a feature in that all of the data bits or a block of data bits in the flash memory can be erased or written at the same time. A flash memory is a large capacity memory whose data is rewritable for a number of times. A flash memory has such functional modes as a data read mode, a data write mode (program mode), a write data verify mode (program verify mode), an erase mode, and other functional modes.
The function in these modes is controlled by writing a specific command corresponding to each of the modes in a controller within the flash memory from the external source by a timing of a write enable (WE) signal. The flash memory does not have an exclusive terminal for writing these commands, and thus, shares a data terminal of the memory to write the commands. The switching between the data and the command is performed by, for example, changing a voltage of a specific voltage supply. In this patent specification, the present invention is explained in detail mainly with respect to the write function, but it can be similarly applied to the erase function of the flash memory as well.
In writing the data in each address, because of the unique physical structure, a flash memory does not necessarily succeed data writing in one write operation. Rather, a plurality of write operation must be repeated several times until the data successfully stored in the designated address. The number of repetition required for the successful data writing (heretofore "writing number") is different from address to address even when the kind of flash memory to be tested (heretofore "MUT") is the same.
In testing the flash memories, for the reasons of achieving longer life times, the data write operation should not be repeated for the addresses that have already experienced the successful data writing. In the data writing test, the MUT is judged as "good quality" when the data writing is successfully completed in the memory cells of all of the addresses within a predetermined number such as 25 times of the write operation.
FIG. 4 is a schematic diagram showing a flash memory test system in the conventional technology. In general, a memory test system supplies test data (write data), control data and address data to a flash memory under test to write the test data in the specified address of the flash memory. The data stored in the flash memory is then read out and compared with expected data, which is usually the same as the write data, and the comparison results are stored in a fail analysis memory with respect to each address of the flash memory for failure analysis.
In FIG. 4, the flash memory test system includes an engineering work station (EWS) 10 and a test processor 11 which are connected to a tester hardware through a tester bus. The tester hardware includes a timing generator 12, a pattern generator 13, a wave formatter 14, a driver 15, an analog comparator 16, a logic comparator 17 and a fail analysis memory 18. A flash memory 5 to be tested (MUT) is connected to the driver 15 and the analog comparator 16.
The work station EWS 10 functions as a user interface controller while the test processor 11 controls the overall operation of the test system. Based on a start command from the EWS 10, the test processor 11 starts the test operation. Sending and receiving of control signals or data signals is performed between each unit through the tester bus. The timing generator 12 generates clock timing signals which determine the overall timings of the test system and sends the clock timing signals to the pattern generator 13.
The pattern generator 13 generates a control signal CS such as WE (write enable) signal, a test pattern data signal TPD and an address signal ADRS to be supplied to the MUT 5, and an expected value pattern to be supplied to the logic comparator 17. The address signal ADRS is also supplied to the fail analysis memory 18. The wave formatter 14 converts the wave shapes of the logic signals from the pattern generator 13 to appropriate wave forms such as RZ (return-to-zero), NRZ (non-return to zero) or EOR (exclusive OR) wave forms. The wave formatter 14 then gives the wave formatted logic signals to the MUT 5 through the driver 15.
In this manner, in the write operation, the test data TPD is written in the address of the MUT 5 defined by the address data ADRS when the control data CS indicates write cycles. In the read operation, the resultant data in the address of the MUT 5 is examined by reading the data therein. In the read operation, the control data CS shows read cycles, and the address data ADRS defines the address of the MUT 5 whose data to be examined.
The resultant data from the MUT S is compared by the analog comparator 16 with reference voltages to determine the logical levels of the read out data. The output of the analog comparator 16 is provided to the logic comparator 17 wherein it is compared with the expected data from the pattern generator 13. The logic comparator 17 determines whether the stored data in the MUT 5 logically coincides with the expected data, and the comparison results are sent to the fail analysis memory 18.
The fail analysis memory 18 gives a write enable inhibit signal /WE to the wave formatter 14 for the address of the MUT 5 whose stored data agrees with the expected data, thereby prohibiting the system from repeating the write operation for the same address any further. The write operation is repeated for the remaining addresses whose data does not agree with the expected data until the stored data agrees with the expected data or until the predetermined maximum numbers of write operation have been performed.
During this repeated write and read process, in case where all of the addresses attain PASS (match) results, the process terminates by sending an MF (match flag) signal from the fail analysis memory 18 to the pattern generator 13. Alternatively, when the writing test is repeated until the predetermined maximum number of times, the process terminates and proceeds to the next test. The fail analysis memory 18 stores the results of the data writing test to be used in the fail analysis stage of the MUT 5.
After the predetermined numbers of the writing test are completed for all of the addresses of the MUT 5, the EWS 10 acquires the content of the fail analysis memory 18 through the test bus and the test processor 11. Based on the information from the failure analysis memory 18 that is read out, the failure information is shown on a display of the work station EWS 10. Although not shown, the failure information is shown, for example, in a bit-map display for each address or each bit. As an example, a failure map that shows a blank for each satisfactory address, and shows character F for each defective address of the MUT 5.
FIG. 5 is a timing chart for explaining the procedure of the writing test for the flash memory by the memory test system of FIG. 4. FIG. 6 is a flow chart showing the procedure of the writing test. With reference to FIGS. 5 and 6 in combination with FIG. 4, the operational procedure of the writing test of the flash memory is further explained below. In this example, it is explained for the case where the MUT 5 has a controller therein to compare the data in the specified address of the MUT 5 with the test data (expected data) and generate a fail signal when both data disagree with each other.
The timing chart of FIG. 5 shows three logic signals to be transmitted from the wave formatter 14 to the MUT 5. The address of the MUT 5 is specified by the address signal ADRS of FIG. 5A from the wave formatter 14. The write enable signal WE of FIG. 5B is provided to the MUT 5 through the control signal CS. When the write enable signal WE is low, the write operation of the MUT 5 is effective. The test data TPD of FIG. 5C is transmitted to the MUT 5 to be written therein.
First, a command signal for the program setup mode is sent through the test pattern data TPD to set the MUT to the program (data write) mode. Then, test data is transmitted to the MUT 5 to write the test data in the address specified by the address ADRS. Then the program verify mode is set to verify the data in the specified address while maintaining the test data during the verify mode. The controller in the flash memory 5 reads the data in the specified address and compares the data with the test data, i.e., the expected data. When they do not match with one another, the write operation for the address is considered to be failure and a program fail signal is output from the MUT 5. This process is repeated for all of the addresses of the MUT 5.
FIG. 6 is a flow chart of the above-explained writing test. As noted above, because of the unique physical structure of a flash memory, one cycle of the write test does not necessarily pass all the addresses. Hence, the similar test procedure is repeated several times after the first cycle of the writing test. Further, in testing a flash memory, it is usually required that the write operation be suspended for the addresses that are already successful in writing the data therein. Hence, by referring to the fail analysis memory 18 that stores test results up to the last test cycles, the write enable inhibit signal /WE is transmitted to the wave formatter 14 for the addresses that have already passed the writing test, so that the write enable signal WE is prohibited from reaching the MUT 5.
In FIG. 6, upon starting the writing test, RETRY is set to "1" in the step S1, and the address ADD is set to "0" in the step S2. Then, in the step S3, it is determined whether PROGRAM, i.e., the data writing for the first address of the MUT 5 has been completed. If it is not completed, PROGRAM (data writing) starts in the step S4, and in the VERIFY step S5, the data in the designated address is compared with the expected data.
In the step S3, if the answer is "yes", i.e., the data writing is completed, the write enable WE is masked based on the write enable inhibit signal /WE from the fail analysis memory 18 to prohibit the system from writing the data in the same address. Then, in the step S7, it is determined whether the address in question is the maximum address. If it is not, the address number is added by one in the step S8 and the process goes back to the step S3 to repeat the process in the steps S3-S7.
If the address in question is the maximum address in the step S7, then it is determined whether all the addresses of the MUT 5 are successful in the data writing in the step S9. In case where not all of the addresses are successful, it is determined whether the number of RETRY reaches the predetermined maximum number in the step S10. If the answer is "no", RETRY is added by one in the step S11 and the whole process in the foregoing is repeated. If the answer in the step S10 is "yes" or all of the addresses in the MUT are successful in the data writing in the step S7, the work station EWS 10 reads the data in the fail analysis memory 18 in the step S12 and determines whether all the data indicate "PASS" in the step S13. If the answer is "yes", the MUT 5 is judged as a good device, if "no" it is a defective device.
The pass/fail test for a flash memory can be sufficiently achieved by the conventional test system in the foregoing. However, flash memories have a limited life-span since it is basically a read-only memory that are rewritable. The number of times for rewriting data therein is limited, and such numbers of times vary from device to device. Hence, if it is possible to anticipate the number of possible rewrite operation in the write/erase cycles, a value of the flash memory will be increased. The value of the flash memory is further increased if the numbers of possible rewrite operation can be increased.
It is known in the art that one of the factors that affects the number of possible data rewriting in flash memories is the uniformity in the manufacturing process of the flash memories. Moreover, the uniformity in the manufacturing process of the flash memories correlates to the number of times required for the successful data writing in the flash memories. The minimum number of the possible write/erase cycles can be predicted from this uniformity. Further, based on the manufacturing uniformity, it is considered that the life times of the flash memories can be prolonged.